Embedded Platform Architecture
Remove Asmedia USB Host Controller Driver. Asmedia USB Host Controller Driver is a software program developed by Asmedia Technology. The most common release is 1.16.26.1, with over 98% of all installations currently using this version. The setup package generally installs about 6 files and is usually about 2.81 MB (2,950,308 bytes). Intel® USB 3.0 eXtensible Host Controller Driver for Intel® 8/9/100 Series and Intel® C220/C610 Chipset Family Installs Intel® USB 3.0 eXtensible Host Controller Driver (version 5.0.4.43v2) for Intel® 8 Series/C220 Series Chipset Families and 4th Generation Intel® Core™ Processor U-Series Platform.
Peter Barry, Patrick Crowley, in Modern Embedded Computing, 2012
Programming Interface
The programming interface for USB host controllers has been standardized. These standards define the register maps for the controller and the descriptor formats for the data when they are transmitted and received on the bus. Three standards are in existence:
UHCI – Universal Host Controller Interface standardized by Intel and used for USB 1.x controllers.
OHCI – Open Host Controller Interface for USB 1.x. This standard was developed by Compaq, Microsoft, and National Semiconductor (ftp://ftp.compaq.com/pub/supportinformation/papers/hcir1_0a.pdf). The OHCI specification expects more capabilities in the hardware over that expected by a UHCI controller.
EHCI – Extended Host Controller Interface. This is used for USB 2.0 device controllers on Intel platforms (http://www.intel.com/technology/usb/ehcispec.htm).
USB OTG – As we mentioned, there is no standard host controller interface standard for the device model.
Most devices support both 1.1 and 2.0 devices by instantiating both a UHCI and EHCI controller. This is often done for expedience; the two controllers can coexist and a multiplexing function can be placed between the devices and each controller.
Depending on the source of the IP in the embedded SOC device, the register map and descriptor format may not follow these standards.
Figure 4.19 shows the components of a software stack on top of the EHCI controller.
The EHCI host controller manages the transmission and reception of frames on the bus. The Enhanced USB host controller contains two sets of software accessible hardware registers, memory-mapped registers, and optional PCI configuration registers. The PCI configuration registers are required if the host controller is implemented as a PCI device. The PCI registers contain the PCI header and some additional configuration registers required to allocate the appropriate system resources during enumeration. The PCI registers are not used by the USB driver after enumeration.
The memory-mapped registers are divided into two sections:
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Capability registers are a set of read-only capability registers. The capability registers specify the limits, restrictions, and capabilities of a host controller implementation. These values are used as parameters to the host controller driver.
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Operational registers (which are read/write). The operational registers are used by system software to interact with the operational state of the host controller. The operation registers contain pointers to lists in host memory that are used to define the traffic to be transmitted and received.
Figure 4.20 shows the register structure for a PCI ECHI controller.
The EHCI provides support for two categories of transfer types: asynchronous and periodic. Periodic transfer types include both isochronous and interrupt. Asynchronous transfer types include control and bulk. Figure 4.20 illustrates that the EHCI schedule interface provides separate schedules for each category of transfer type. The periodic schedule is based on a time-oriented frame list that represents a sliding window of time of host controller work items. All isochronous and interrupt transfers are serviced via the periodic schedule. The asynchronous schedule is a simple circular list of schedule work items that provides a round-robin service opportunity for all asynchronous transfers.
Note
Wake on USB: The ECHI specification often describes the physical location of the registers within the device. Different parts of the ECHI controller are powered by different supply voltages within the SOC. As a result, some sets of registers retain their values during different CPU power states. These features are provided to support wakeup events from a USB device. Consider the case where your laptop is in a sleep state (suspended); moving the mouse can trigger a wakeup event to the platform, but in order to do so the ECHI controller must remain powered.
The ECHI controller generates interrupts to the processor based on a number of events. One such interrupt is generated at a point in the processing of the asynchronous lists. This is configured when the list is generated by the driver to provide enough advanced notice for the driver to add more work to the list. Another interrupt is generated when the period frame list rolls over; this again is to ensure that the driver supplies data for subsequent frames.
As we mentioned, there are two key lists managed by the driver and consumed by the host controller: the periodic frame list (for isochronous and interrupt traffic) and the asynchronous list (control and bulk transfers). We’ll discuss the asynchronous list first. The list is only processed when the host controller reaches the end of the periodic list, the periodic list is disabled, or the periodic list is empty. That is, it has the lowest priority of all traffic and will only be sent on the bus when there is no other work to do. The asynchronous list is pointed to by a control register: AsyncListAddress. The list is a circular list of queue heads. The controller cycles through each element in the list (in a round-robin fashion), processing each queue head as it goes. One queue head is used to manage the data stream for one endpoint. The queue head consists of a queue element transfer descriptor. The queue head structure contains static endpoint characteristics and capabilities. It also contains a working area from where individual bus transactions for an endpoint are executed. Each queue element transfer descriptor represents one or more bus transactions, which is defined in the context of this specification as a transfer. A descriptor has an array of buffer pointers, which is used to reference the data buffer for a transfer. Figure 4.21 shows how the elements described above are linked together.
The USB UHCI device driver provides services to the individual class drivers, which make use of the bus drive to transmit and receive data.
Available in this download are drivers for VIA USB 2.0 host controller on a system running on Windows 98/98SE/Me. Due to licensing agreements, USB 2.0 drivers for Windows 2000/XP are not available for download. They are supplied on CD with new mainboards or available through Windows Update. This version is a bug-fixing release.